Project Light Alarm with Time Controller

 Project Title: Light Alarm with Time Controller             BSIT 3A

 Members:
              Kevin John Porras

              Jenny Zarate

              Arnie Joy Tabasundra
              Jenny Mae Porras

May 14, 2014

A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time. The clock inputs of all the flip-flops are connected together and are triggered by the input pulses.  Thus, all the flip-flops change state simultaneously (in parallel).  The circuit below is a 3-bit synchronous counter.  The J and K inputs of FF0 are connected to HIGH.  FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.

  
The result is a four-bit synchronous "up" counter. Each of the higher-order flip-flops are made ready to toggle (both J and K inputs "high") if the Q outputs of all previous flip-flops are "high." Otherwise, the J and K inputs for that flip-flop will both be "low," placing it into the "latch" mode where it will maintain its present output state at the next clock pulse. Since the first (LSB) flip-flop needs to toggle at every clock pulse, its J and K inputs are connected to V_cc or V_dd, where they will be "high" all the time. The next flip-flop need only "recognize" that the first flip-flop's Q output is high to be made ready to toggle, so no AND gate is needed. However, the remaining flip-flops should be made ready to toggle only when all lower-order output bits are "high," thus the need for AND gates. 

Asynchronous counter , Since we know that binary count sequences follow a pattern of octave (factor of 2) frequency division, and that J-K flip-flop multivibrators set up for the "toggle" mode are capable of performing this type of frequency division, we can envision a circuit made up of several J-K flip-flops, cascaded to produce four bits of output. The main problem facing us is to determine how to connect these flip-flops together so that they toggle at the right times to produce the proper binary sequence. Examine the following binary count sequence, paying attention to patterns preceding the "toggling" of a bit between 0 and 1: 


 

















Starting with four J-K flip-flops connected in such a way to always be in the "toggle" mode, we need to determine how to connect the clock inputs in such a way so that each succeeding bit toggles when the bit before it transitions from 1 to 0. The Q outputs of each flip-flop will serve as the respective binary bits of the final, four-bit count:  

he first flip-flop (the one with the Q₀ output), has a positive-edge triggered clock input, so it toggles with each rising edge of the clock signal. Notice how the clock signal in this example has a duty cycle less than 50%. I've shown the signal in this manner for the purpose of demonstrating how the clock signal need not be symmetrical to obtain reliable, "clean" output bits in our four-bit binary sequence. In the very first flip-flop circuit shown in this chapter, I used the clock signal itself as one of the output bits. This is a bad practice in counter design, though, because it necessitates the use of a square wave signal with a 50% duty cycle ("high" time = "low" time) in order to obtain a count sequence where each and every step pauses for the same amount of time. Using one J-K flip-flop for each output bit, however, relieves us of the necessity of having a symmetrical clock signal, allowing the use of practically any variety of high/low waveform to increment the count sequence.
 

Pin Configuration

May 5 2014

labact1

  In electronics, a logic gate is an idealized or physical device implementing a boolean function that is, it performs a logical operation on one or more logical inputs, and produces a single logical output. Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device.

A truth table is a mathematical table used in logic—specifically in connection with Boolean algebra, boolean functions, and propositional calculus—to compute the functional values of logical expressions on each of their functional arguments, that is, on each combination of values taken by their logical variables (Enderton, 2001). In particular, truth tables can be used to tell whether a propositional expression is true for all legitimate input values, that is, logically valid. 


A schematic, or schematic diagram, is a representation of the elements of a system using abstract, graphic symbols rather than realistic pictures. A schematic usually omits all details that are not relevant to the information the schematic is intended to convey, and may add unrealistic elements that aid comprehension. For example, a subway map intended for riders may represent a subway station with a dot; the dot doesn't resemble the actual station at all but gives the viewer information without unnecessary visual clutter. A schematic diagram of a chemical process uses symbols to represent the vessels, piping, valves, pumps, and other equipment of the system, emphasizing their interconnection paths and suppressing physical details. In an electronic circuit diagram, the layout of the symbols may not resemble the layout in the physical circuit. In the schematic diagram, the symbolic elements are arranged to be more easily interpreted by the viewer.

Logic Gates and Truth Tables

Type	Distinctive shape	Rectangular shape	Boolean algebra between A & B	Truth table
AND			or &	INPUT OUTPUT A B A AND B 0 0 0 0 1 0 1 0 0 1 1 1
OR				INPUT OUTPUT A B A OR B 0 0 0 0 1 1 1 0 1 1 1 1
NOT			or ~	INPUT OUTPUT A NOT A 0 1 1 0

NAND			or	INPUT OUTPUT A B A NAND B 0 0 1 0 1 1 1 0 1 1 1 0
NOR			or	INPUT OUTPUT A B A NOR B 0 0 1 0 1 0 1 0 0 1 1 0
XOR				INPUT OUTPUT A B A XOR B 0 0 0 0 1 1 1 0 1 1 1 0
XNOR			or	INPUT OUTPUT A B A XNOR B 0 0 1 0 1 0 1 0 0 1 1 1

 

 The 7400 series of transistor–transistor logic integrated circuits are the most popular family of TTL integrated circuit logic. Quickly replacing diode–transistor logic, it was used to build the mini and mainframe computers of the 1960s and 1970s. Several generations of pin-compatible descendants of the original family have since become de facto standard electronic components.

References: http://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits
                    http://electronicsclub.info/74series.htm

I1 = V/R1 = 24/6 = 4 A

I2= V/R2 = 24/12 = 2 A

I3 = V/R3 = 24/10 = 2.4 A

IT (I1+ I2 + I3) = 4+2+2.4 = IT 8.4 A

1) BLUE BLUE RED GOLD

66 * 100 = ± 5%

6600 * 0.5 = 3300 Ω

6600 + 3300 = 9900 Ω

6600 – 3300 = 3300 Ω

Range = 3300 to 9900 Ω

2) GREEN BLUE RED SILVER

56 * 100 = ± 10%

5600 * 0.10 = 560 Ω

5600 + 560 = 11200 Ω

5600 - 560 = 5040 Ω

Range = 5040 to 11500 Ω